1. Field of the Invention
This invention relates to a metal-oxide-semiconductor (MOS) device manufacturing process, and more particularly to a method of reducing gate insulator defects caused by both photo-resist residues and ion implant damage.
2. Related Art
In conventional complementary metal-oxide-semiconductor (CMOS) manufacturing processes, ions are implanted in the active regions to adjust the threshold voltage of the P-channel and N-channel transistors, to be formed thereon. These threshold adjust implants are performed after the gate insulator layer is formed. Typically, the gate insulator layer is formed by thermal oxidation of the silicon in the active regions.
FIGS. 5A-5E show cross-sectional views of a wafer processed through the various manufacturing steps of a conventional CMOS manufacturing process. These figures show a semiconductor substrate 41, an N-well 42, a P-well 43, thick field oxide 44a for separating active regions 44b, a gate oxide layer 45, patterned photo-resist layers 46, 47, ion implant of BF.sub.2.sup.+ ions 48, and a gate electrode layer 49.
In this example, semiconductor substrate 41 is a P-type silicon substrate with a &lt;100&gt; planar surface. N-well 42 is formed through the ion implantation of phosphorous. P-well 43 is formed through the ion implantation of boron. After the N-well and P-well implants, four hours of thermal processing takes place at 1,200.degree. C. in a mixed gas atmosphere of nitrogen and oxygen in a ratio of 9:1. After driving in N-well 42 and P-well 43, thick field oxide regions 44a are formed (separated by active regions 44b), followed by formation of a 150 .ANG. gate oxide layer 45 as shown in FIG. 5A.
Most CMOS integrated circuits have both N-channel and P-channel transistors (MOSFETs) fabricated on a single semiconductor substrate. In order to form both types of MOSFETs on a single substrate requires that certain process steps be performed only upon the regions intended to contain transistors of one conductivity type or the other. For example, because the p-type source/drain junctions of P-channel transistors are typically formed by a boron implant, this implant must be masked from the areas containing the N-channel transistors. Similarly, because the n-type source/drain junctions of N-channel transistors are typically formed by an arsenic implant, this implant must be masked from the areas containing the P-channel transistors. There are other process steps that are appropriate only for one or the other conductivity type MOSFET. The process description below includes steps for isolating P-channel transistor formation activity from N-channel transistor formation activity.
Referring to FIG. 5B, resist layer 46 is formed over gate oxide layer 45. This layer has an opening for an area that will become the channel regions of the N-channel transistors. Channel doping with BF.sub.2.sup.+ ions 48 takes place under the conditions of 40 keV and 1.0.times.10.sup.12 /cm.sup.2. This channel doping takes place so that the N-channel MOS transistor threshold voltage can be adjusted upward. Therefore, ions such as BF.sub.2.sup.+ ions or B.sup.+ ions are used.
Resist layer 46 is stripped by immersion in a mixed solution of heated sulfuric acid and a hydrogen peroxide. After removing resist layer 46, resist layer 47 is formed, as shown in FIG. 5C. Resist layer 47 has openings that will become the channel regions of P-channel transistors. Channel doping with BF.sub.2.sup.+ ions 48 takes place under the conditions of 40 keV and 1.8.times.10.sup.12 /cm.sup.2. This channel doping ion implant takes place so that the P-channel transistor threshold voltage can be adjusted upward. Ions such as BF.sub.2.sup.+ ions and B.sup.+ ions are used in the same manner. Resist layer 47 also is removed by immersion in a mixed solution of heated sulfuric acid and hydrogen peroxide, resulting in the structure shown in FIG. 5D.
Notwithstanding the resist stripping process, the inorganic oxides of the resist material will not dissolve in the sulfuric acid and, therefore, will remain. This residue will be unevenly distributed on the surface of gate oxide layer 45 at a thickness of from 5 .ANG. to 10 .ANG.. The removal of the residue takes place through etching in a hydrogen fluoride solution. For example, it takes place through etching for ten seconds in HF:H.sub.2 O=1:200.
Referring to FIG. 5E, a polycrystalline silicon layer about 4,000 .ANG. thick is formed as gate electrode layer 49. Through the diffusion of N-type ions, the polycrystalline silicon layer is made into an N-type polycrystalline silicon layer.
Subsequently, conventional manufacturing process steps are used to produce a CMOS integrated circuit (IC).
In conventional manufacturing as described above, the threshold adjust implant is done after gate oxide formation, but before gate electrode formation. The gate oxide layer is typically damaged as a result of the ion implantation.
The damage to the gate oxide layer is depicted in FIG. 6 which shows implant profile 50 and defect layer 51. R.sub.p, which is the peak depth of the ion implantation, is 370 .ANG. at an energy of 40 keV. The region from 60% to 70% of R.sub.p is the layer in which defects will appear easily. Defect layer 51 represents this. In this case, the depth of the implant-induced defect has reached 220 .ANG.. If the thickness of gate insulation layer 45 is 150 .ANG., there will be a lot of defects within gate insulation layer 45.
In addition, in the resist application and removal process steps before and after ion implantation, there are about 5 .ANG. to 10 .ANG. of particles that remain on the gate insulation layer, for example, particles such as Al.sub.2 O.sub.3 or MgO. The surface of the gate oxide layer is etched about 10 .ANG. in the etching process step that uses the hydrogen fluoride solution described above. The entire gate oxide layer becomes thinner and, at the same time, deep etching occurs in some places, causing defects.
As the degree of integration increases, the gate oxide layer becomes thinner. For example, in a 0.8 micron process, gate oxide thickness is from 150 .ANG. to 180 .ANG.. In a 0.5 micron process, gate oxide thickness is from 120 .ANG. to 150 .ANG.. In a 0.3 micron process, gate oxide thickness is from 100 .ANG. to 120 .ANG.. As a consequence of the reduction of gate insulator thickness, the gate insulator becomes more sensitive to the defect mechanisms described above.